The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a feature in its isolation structure, and a method of fabricating an isolation region of the semiconductor device.
An isolation structure useful in realizing scale down of semiconductor element structures has been required along with a high degree of integration of semiconductor devices. In recent years, a shallow trench isolation (STI) structure suitable for a finer isolation structure has been used instead of the conventional Local Oxidation of Silicon (LOCOS) structure. Proposals for various problems of the STI structure have been made for a generation in and after the 45 nm generation.
For example, a semiconductor device having an STI stricture in which a SiN film is formed as a liner film on an inner wall of a trench portion, and a polysilazane-spin on glass (P-SOG) film and an element insulating film are disposed in an upper side and a lower side of the trench portion, respectively, thereby obtaining a two-layer structure is known as conventional one. This semiconductor device, for example, is described in a non-patent literary document 1 of Jin-Hwa Heo, “Void Free and Stress Shallow Trench Isolation Technology using P-SOG for sub 0.1 μm Device”, 2002 Symposium on VLSI Technology Digest of Technical Papers. In this semiconductor device, the P-SOG film is disposed as an upper layer of the trench portion, which results in that it is possible to realize an improvement in productivity, relaxation of a stress, and reduction of voides.
In addition, a semiconductor device having an STI structure in which SiO2 films are formed in an upper side and a lower side of a trench portion by utilizing a plasma CVD method and a spin coating method, respectively, thereby obtaining a hybrid structure, for example, is known as another conventional one. This semiconductor device, for example, is described in a non-patent literary document 2 of K. Ota, “Stress Controlled Shallow Trench Technology to Suppress the Novel Anti-Isotropic Impurity Diffusion for 45 nm-node High-Performance CMOSFETs”, 2005 Symposium on VLSI Technology Digest of Technical Papers. In this semiconductor device, a stress direction can be controlled by the SiO2 film formed as the lower layer of the trench portion by utilizing the spin coating method, and an operating current of each of an n-channel FET and a p-channel FET can be improved by up to 20%. In addition, a leakage current caused to flow through a junction portion is improved because a compressive stress due to the STI structure is reduced by a stress relaxing function of the SiO2 film which is formed as the lower layer of the trench portion by utilizing the spin coating method.
However, in order to suppress the leakage current caused to flow through the junction portion in the STI structure as described above, it is necessary to prevent the compressive stress from being increased by thinning the SiO2 film which is formed as the upper layer of the STI structure by utilizing the plasma CVD method. On the other hand, this semiconductor device involves a problem that the liner film is formed near each of a source region and a drain region, thereby deteriorating short channel characteristics.